Semiconductor Device

ABSTRACT

Regarding a semiconductor device, especially the present invention suppresses disconnection of the connection structure concerned in the semiconductor device which has the electric and mechanical connection structure using solder, and aims at improving connection reliability. And to achieve the above objects, the semiconductor device has the solder bump which electrically connects a semiconductor chip and a package substrate, the under-filling resin with which it filled up between the semiconductor chip and the package substrate, and a solder ball which electrically connects a package substrate with the outside, and the solder bump&#39;s elastic modulus is made lower than the elastic modulus of a solder ball.

INCORPORATION BY REFERENCE

The present application claims priority from PCT applicationPCT/JP2004/018579 filed on Dec. 13, 2004, the content of which is herebyincorporated by reference into this application.

TECHNICAL FIELD

The present invention relates to a semiconductor device and relates tothe semiconductor device which has the electric and mechanicalconnection structure using solder especially.

BACKGROUND ART

Flip chip bonding is known as one of the assembly technology of asemiconductor device. This bonding method is a method which sticks theconnection pad (only henceforth a “pad”) formed in the under surface ofthe semiconductor chip, and the pad formed in the package substrateupper surface, applies heat and pressure, and is joined. On each pad ofa semiconductor chip and a package substrate, the solder bump of ballstate is beforehand formed in the case. Usually, the solder bump is putin order in a lattice manner, and such a structure is called BGA (BallGrid Array) structure.

Conventionally, Sn(tin)-Pb (lead) eutectic solder was used as solderused for a solder bump. However, in recent years, in order to inhibitthe bad influence to the environment at the time of doing disposaltreatment of the electronic parts, the so-called lead free solder thatdoes not include Pb as a solder alloy is used widely.

As lead free solder used for a solder bump, the solder alloy of theso-called “Sn—Ag—Cu system” which comprises Sn, Ag (silver), and Cu(copper) is known widely. The solder alloy which consists of Ag:3-4 mass%, Cu:0.5-1.0 mass %, and Sn as the remainder especially was common.However, the solder alloy for solder bumps which did not use Agexpensive in material price so much (below 2 mass %), but was excellentin joining reliability and dropping impact-proof nature is also proposed(for example, following Patent Reference 1).

In connection with the microfabrication of a semiconductor chip, the padsize of the semiconductor chip is also small. Therefore, a solder bump'svolume and the junction area of a solder bump and a pad will becomesmall inevitably, and the strength of a junction portion will fall.Usually, in order to compensate it, both gap is filled up withunder-filling resin, such as an epoxy resin, after doing bonding of thesemiconductor chip to a package substrate. Under-filling resin pastes upbetween a semiconductor chip and a package substrate, and it makes theexternal force concerning a solder bump's junction ease.

On the other hand, the electrode for external connection is formed inthe under surface of the package substrate of a semiconductor device.The solder ball used when mounted in mounting substrates, such as amother board of a computer, on it is formed. And when mounted, thesemiconductor device concerned is soldered to a mounting substrate bymounting a semiconductor device on a mounting substrate and heating(reflowing) it so that a solder ball may contact the connection pad of amounting substrate.

Usually, so that it may not melt with heating of an assembling step, asfor the solder bump as internal wiring which connects a semiconductorchip and a package substrate, what has a melting point higher than thesolder ball as external wiring under a package substrate is used. Byusing what has a small ratio over the volume at the time of solid of thevolume difference of a volume at the time of solid and a volume at thetime of melting as a solder bump's material, even when it melts withheating at the time of mounting, there is also technology of preventingthe short circuit between solder bumps (for example, following PatentReference 2).

For convenience of explanation, the solder bump as internal wiring whichconnects a package substrate with a semiconductor chip may be hereaftercalled an “inner bump”, and the solder ball as external wiring whichconnects a package substrate with the outside (mother board etc.) may becalled an “outer ball”.

[Patent Reference 1] Japanese Unexamined Patent Publication No.2002-239780

[Patent Reference 2] Japanese Unexamined Patent Publication No.2004-207494

Although the coefficient of thermal expansion of the semiconductor chipof common silicon is about 7 ppm/° C. here, the package substrate andmounting substrate of resin are about 20 ppm/° C., and under-fillingresin of an epoxy resin is about 30 ppm/° C., solder is about 15 ppm/°C. and they differ from each other, respectively. Therefore, by atemperature change, internal stress occurs in a part between thesemiconductor chips and package substrates inside a semiconductordevice, and for the connecting part between the package substrate andmounting substrate at the time of mounting. The stress was applied tothe inner bump or the outer ball, became a factor which causesdisconnection, and was reducing the connection reliability of thesemiconductor device.

DISCLOSURE OF THE INVENTION

The present invention aims at offering the semiconductor device which ismade in order to solve the above problems and which can suppress thedisconnection by stress of connection structure using solder, and canacquire high connection reliability.

A semiconductor device concerning the present invention comprises asemiconductor chip, a package substrate over which the semiconductorchip is mounted, a solder bump which electrically connects thesemiconductor chip and the package substrate, under-filling resin whichfills up between the semiconductor chip and the package substrate, and asolder ball which electrically connects the package substrate with anoutside, wherein the solder bump's elastic modulus is lower than anelastic modulus of the solder ball.

According to the semiconductor device concerning the present invention,since the elastic modulus is low, the inner bump can buffer the stressresulting from the difference in the coefficient of thermal expansion ofa solder bump and under-filling resin. Therefore, the stressconcentration to the connection portion of a solder bump and asemiconductor chip and the connection portion of a solder bump and apackage substrate can be eased. Since the elastic modulus is high, thesolder ball can hold the stress applied from the outside as selfinternal stress. Therefore, a solder ball can absorb the stressresulting from the difference in the coefficient of thermal expansion ofa package substrate, and the mounting substrate which does externalconnection at the time of mounting, and the stress concentration to theperipheral part of a package substrate is eased. Therefore,disconnection between a package substrate and a mounting substrate canbe suppressed. As a result, the connection reliability of the internalwiring of a semiconductor device and the connection reliability withexternal wiring at the time of mounting can be improved.

The purpose, the feature, aspect, and advantage of this invention becomeclearer with the following detailed explanation and accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a drawing showing the structure of the semiconductor deviceconcerning an embodiment;

FIG. 2 is an enlarged sectional view of the connection portion of asemiconductor chip and a BGA substrate in the semiconductor deviceconcerning an embodiment;

FIG. 3 is a drawing showing the semiconductor device structure at thetime of mounting;

FIG. 4 is a flow diagram showing the manufacturing method of thesemiconductor device concerning an embodiment; and

FIGS. 5A to 13 are process charts for explaining the manufacturingmethod of the semiconductor device concerning an embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 is a drawing showing the structure of the semiconductor deviceconcerning an embodiment of the invention. The semiconductor device 1concerned has BGA structure, and BGA substrate (package substrate) 20 isequipped with semiconductor chip 10 by the face down method. On theunder surface (integrated circuit surface), semiconductor chip 10 has aplurality of first pads 11. BGA substrate 20 has a plurality of secondpads 21 as an internal electrode on the upper surface (mounting surfaceof semiconductor 1 chip). Both first pad 11 and second pad 21 areconnected to solder bump (inner bump) 31 electrically and mechanically.Thereby, it electrically connects with BGA substrate 20, andsemiconductor chip 10 is fixed mechanically.

The gap of semiconductor chip 10 and BGA substrate 20 is filled up withunder-filling resin 32, such as an epoxy resin. Under-filling resin 32pastes up between semiconductor chip 10 and BGA substrates 20, and itfunctions as easing the external force concerning the junction portionof first pad 11 and second pad 21, and inner bump 31.

The enlarged view for a connecting part of semiconductor chip 10 and BGAsubstrate 20 is shown in FIG. 2. Although the illustration by FIG. 1 wasomitted, passivation film 12 is formed in the under surface ofsemiconductor chip 10, and it has structure that the front surface offirst pad 11 exposes to the opening formed in the passivation film 12concerned. At this embodiment, first pad 11 of semiconductor chip 10 isformed with aluminum. Since aluminum does not get wet easily in solder,like FIG. 2, under bump metal (UBM) 13 (first metallic film) withsufficient wettability with solder is formed in the front surface offirst pad 11, and inner bump 31 connects with first pad 11 via the UBM13concerned. Thereby, the connection reliability of first pad 11 and innerbump 31 improves. As UBM13, the thing of the three-layer structure by Ti(titanium), Cu, and Ni is known, for example.

Insulating film 23 (following “solder resist 23”) (second metallic film)called solder resist is formed in the upper surface of BGA substrate 20.It has structure that the front surface of second pad 21 exposes to theopening formed in solder resist 23. Solder resist 23 has prevented thatexcessive solder adheres to the uppermost wiring layer to which thesecond pad 21 concerned belongs in the case of soldering to second pad21. In this embodiment, second pad 21 is formed with copper. Althoughwettability of copper with solder is comparatively good, in the purposewhich prevents a “erosion phenomenon”, coating (plating) 24 by apredetermined metal is performed to the front surface of second pad 21.

An “erosion phenomenon” is a phenomenon in which other metal concernedwill be eroded when other metal is touched, after Sn and Ag have melted.It will become a cause of disconnection when an electrode is eroded bysolder according to this phenomenon. Although Pb plays the role of abarrier and the “erosion phenomenon” of the electrode did not happeneasily in the eutectic solder of the conventional Sn—Pb system, the Pbis not included in lead free solder, and an “erosion phenomenon” becomesremarkable. As coating 24, the thing of the two-layer structure by Ni(nickel) and Au (gold) is known, for example. In this embodiment, sinceinner bump 31 is formed on second pad 21 via coating 24, without formingdirectly on second pad 21, this “erosion phenomenon” is prevented.Thereby, lowering of the connection reliability of second pad 21 andinner bump 31 is suppressed.

A plurality of external electrodes 22 for electrically connectingsemiconductor device 1 with the outside are formed in the under surface(external connection surface) of BGA substrate 20, and solder ball(outer ball) 33 is formed in each of these external electrode 22. Outerball 33 is used for connecting semiconductor device 1 to mountingsubstrates, such as a mother board, electrically and mechanically.

Stiffener (reinforcement) 34 is formed in the BGA substrate 20 uppersurface via adhesive tape 35. As for the material of stiffener 34, whathas a near coefficient of linear expansion with BGA substrate 20 isdesirable, for example, it comprises copper so that the generation ofthe stress resulting from the temperature change by generation of heatof semiconductor chip 10 etc. may be suppressed. Adhesive tape 35 isformed, for example with resin of an epoxy system with high adhesiveproperty.

Heat spreader 36 is formed in the upper part of semiconductor chip 10for the purpose of the improvement in heat radiation property, andprotection of semiconductor chip 10. It fills up with heat radiationresin 37 between heat spreader 36 and semiconductor chip 10. This heatradiation resin 37 is formed with silver paste with high thermalconductivity so that heat spreader 36 and semiconductor chip 10 mayconnect thermally. Heat spreader 36 is fixed also to stiffener 34 viaadhesive tape 38. Adhesive tape 38 is formed, for example with resin ofan epoxy system with high adhesive property.

At the time of the actual use of the semiconductor device 1 concerned,it is mounted on mounting substrate 40 like FIG. 3 by joining outer ball33 to connection pad 41 of the mounting substrate 40 upper surface. Atthis time, under-filling resin is not formed between BGA substrate 20and mounting substrate 40.

In this embodiment, a solder alloy with a low elastic modulus is used asinner bump 31 which connects between semiconductor chip 10 and BGAsubstrates 20, and the solder alloy whose elastic modulus is higher thaninner bump 31 is used as outer ball 33 for external connection. Anelastic modulus is expressed with the ratio of strain and stress whenstress is applied to an object, and is defined by“elastic-modulus=stress/strain.” That is, the solder alloy with a lowelastic modulus is easy to deform with stress, and excellent inductility. On the contrary, the solder alloy with a high elastic moduluscannot deform easily due to stress, and strength is highly excellent infatigue resistance.

Action and the effect that the semiconductor device concerning thisembodiment performs so hereafter are explained.

As stated previously, semiconductor chip 10, BGA substrate 20,under-filling resin 32, solder (inner bump 31 and outer ball 33), andmounting substrate 40 by which external connection is done usually havea coefficient of thermal expansion different, respectively. Therefore,stress occurs into each connection portion by a temperature change.

Between semiconductor chip 10 and BGA substrate 20, mechanicalconnection has accomplished by two, inner bump 31 and under-fillingresin 32. Therefore, the stress resulting from the difference in thecoefficient of thermal expansion of semiconductor chip 10 and BGAsubstrate 20 is not only applied, but the stress of the longitudinaldirection resulting from the difference in the coefficient of thermalexpansion of inner bump 31 and under-filling resin 32 is applied toinner bump 31. That is, although under-filling resin 32 is easing thestress of the horizontal direction applied to inner bump 31, it is afactor which increases the stress of a longitudinal directionconversely.

When a coefficient of thermal expansion is larger than inner bump 31like an epoxy resin in under-filling resin 32, the tensile stress of alongitudinal direction is applied to inner bump 31. The tensile stressconcerned increases especially near the center of semiconductor chip 10by a “warp” of semiconductor chip 10 resulting from the coefficients ofthermal expansion of semiconductor chip 10 and BGA substrate 20differing. The stress cannot be buffered as inner bump 31 is materialwith a high elastic modulus at this time, but stress concentrates on theconnection portion of inner bump 31 and semiconductor chip 10, and theconnection portion of inner bump 31 and BGA substrate 20, and it becomeseasy to generate disconnection in those portions.

When the connection portion of inner bump 31, and semiconductor chip 10and BGA substrate 20 is structure like FIG. 2, it is especially easy togenerate disconnection between first pad 11 and UBM13. Since diameter d1of the opening of passivation film 12 which first pad 11 exposes issmaller than diameter d2 of the opening of solder resist 23 which secondpad 21 exposes (that is, the area of the joint surface (interface) offirst pad 11 and UBM13 is smaller than the area of the joint surface ofsecond pad 21 and coating 24), it is because stress will concentrate onthe interface of first pad 11 and UBM13. Since in other words theelectric connection area to inner bump 31 in first pad 11 front surfaceis smaller than the electric connection area in second pad 21 frontsurface, it becomes easy to disconnect electric connection with firstpad 11 and inner bump 31.

So, in this embodiment, a solder alloy with a low elastic modulus asinner bump 31 is used. Since inner bump 31 with a low elastic modulus iseasy to deform according to stress, it can buffer the tensile stressapplied to inner bump 31. The stress concentration to the connectionportion of inner bump 31 and semiconductor chip 10 and the connectionportion of inner bump 31 and BGA substrate 20 is eased. Therefore,disconnection between semiconductor chip 10 and BGA substrate 20 can besuppressed, and the connection reliability between semiconductor chip 10and BGA substrate 20 improves.

In this embodiment, the exposure area (size of first pad 11) of firstpad 11 is made small like FIG. 2 in order to contribute to highintegration of semiconductor chip 10. According to the presentinvention, since the stress applied to the interface of first pad 11 andUBM13 is eased, even if it makes size of first pad 11 small, lowering ofconnection reliability is suppressed.

Next, outer ball 33 between BGA substrate 20 and mounting substrate 40at the time of mounting is explained. As mentioned above, under-fillingresin is not formed between BGA substrate 20 and mounting substrate 40,but it connects only with outer ball 33. BGA substrate 20 and mountingsubstrate 40 have strength higher than semiconductor chip 10, do notgenerate a “warp” easily, and seldom generate the stress of alongitudinal direction. Therefore, the stress of the horizontaldirection resulting from the difference in the coefficient of thermalexpansion of BGA substrate 20 and mounting substrate 40 is mainlyapplied to outer ball 33. External electrode 22 of BGA substrate 20 andconnection pad 41 of mounting substrate 40 have large size, the area ofthe joint surface of outer ball 33 and them is large, and the strengthto a tensile stress is high from the first. Therefore, to have only thefirmness which can absorb the stress of a horizontal direction isdesired, especially concerning outer ball 33.

Usually, stress resulting from the difference in the coefficient ofthermal expansion of BGA substrate 20 and mounting substrate 40 tends toconcentrate on the peripheral part of BGA substrate 20. When outer ball33 is material with a low elastic modulus, each outer ball 33 willdeform, and stress will not be absorbed, but stress will escape to theperipheral part of BGA substrate 20. Thereby, the stress applied toouter ball 33 of a peripheral part will increase. Outer ball 33 isdamaged by the result, especially at the peripheral part of BGAsubstrate 20, and it becomes easy to generate disconnection.

So, in this embodiment, a solder alloy with a high elastic modulus asouter ball 33 is used. Outer ball 33 with a high elastic modulus cannotdeform easily according to stress, and the stress applied from theoutside can be held as self internal stress. Therefore, each of eachouter ball 33 can absorb the stress resulting from the difference in thecoefficient of thermal expansion of BGA substrate 20 and mountingsubstrate 40, and the stress concentration to outer ball 33 of theperipheral part of BGA substrate 20 is eased. Therefore, disconnectionbetween BGA substrate 20 and mounting substrate 40 can be suppressed,and the connection reliability between BGA substrate 20 and mountingsubstrate 40 improves.

Thus, by using a solder alloy with a low elastic modulus as inner bump31, and using a solder alloy with a high elastic modulus as outer ball33, the connection reliability between semiconductor chip 10 and BGAsubstrate 20 and between BGA substrate 20 and mounting substrate 40 canbe improved.

As mentioned above, the thing of a Sn—Ag—Cu system is common as leadfree solder used for a solder bump and a solder ball. The elasticmodulus of a Sn—Ag—Cu system solder alloy is mostly decided by the ratio(mass %) of Ag included in it. Usually, an elastic modulus becomes highas the ratio of Ag increases. Therefore, what is necessary is to use asolder alloy with few ratios of Ag for inner bump 31, and just to use asolder alloy with many ratios of Ag for outer ball 33, in applying aSn—Ag—Cu system solder alloy as inner bump 31 and outer ball 33 of thisembodiment. Thereby, inner bump's 31 elastic modulus becomes low, andthe elastic modulus of outer ball 33 becomes high.

The present inventor conducted the experiment for acquiring compositionof a solder alloy with high connection reliability. In the experiment,durability test (heat cycle test) to a repetition of a temperaturechange was done about the semiconductor device of structure of havingbeen shown in FIG. 1. As inner bump 31 and outer ball 33, the solderalloy of the Sn—Ag—Cu system was used.

As a result of the experiment, when the ratio of Ag was 0-1.5 mass % asinner bump 31, the outstanding durability was acquired. As outer ball33, in the case that the ratio of Ag is more than 2.5 mass %, desirablymore than 3%, the excellent durability was acquired. “Ag:0 mass %” hasreferred to what (only Cu and Sn are comprised) Ag is not included for.That is, a present inventor found out that when applying the solderalloy of a Sn—Ag—Cu system to the present invention by the experimentconcerned, the high connection reliability of semiconductor device 1 wasacquired by using the thing of Ag of 0-1.5 mass % as inner bump 31, andusing the thing of Ag of 2.5 mass % (desirably 3% or more) as outer ball33.

Next, the manufacturing method of the semiconductor device concerningthe present invention is explained with reference to the flow diagram ofFIG. 4. FIG. 5A-FIG. 13 are the drawings for explaining themanufacturing process concerned. In these FIGS. 5-FIGS. 13, the samereference is given to the same element as what was shown in FIG. 1.

Semiconductor chip 10 which has first pad 11 of aluminum on a frontsurface is first formed like FIG. 5A (S1). FIG. 5B shows the enlargedsection of first pad 11 of semiconductor chip 10 front surface.Passivation film 12 is formed in the front surface of semiconductor chip10, and the opening which first pad 11 exposes is formed in passivationfilm 12.

And like FIG. 6, UBM13 for improving wettability with solder is formedin the front surface of first pad 11 (S2). This UBM13 is formed by doingsputtering of Ti, Cu, and Ni one by one, and patterning after that onsemiconductor chip 10. And like FIGS. 7A and 7B, solder alloy 31 a whichconstitutes inner bump 31 is formed on first pad 11 through UBM13 byscreen printing the soldering paste which comprises Ag:1.0 mass %,Cu:0.5 mass %, and remainder Sn (S3).

Apart from the above-mentioned step, BGA substrate 20 which has secondpad 21 for connecting with semiconductor chip 10 and external electrode22 for connecting outside (mounting substrate) is formed like FIG. 8A(S4). FIG. 8B shows the enlarged section of second pad 21 of BGAsubstrate 20 front surface. Solder resist 23 is formed in the frontsurface of BGA substrate 20, and an opening which second pad 21 exposesto solder resist 23 is formed.

And like FIG. 9, coating 24 which prevents the “erosion phenomenon” ofsecond pad 21 by solder is formed. This coating 24 is formed on secondpad 21 by forming Ni and Au one by one by electroless plating (S5). Andlike FIGS. 10A and 10B, solder alloy 31 b which constitutes inner bump31 is formed on second pad 21 through coating 24 by screen printing ofthe soldering paste which comprises Ag:1.0 mass %, Cu:0.5 mass %, andremainder Sn (S6).

And solder alloy 31 a of semiconductor chip 10 and solder alloy 31 b ofBGA substrate 20 are stuck like FIG. 11, and the so-called flip chipjunction that applies heat and pressure and is joined is performed (S7).When solder alloy 31 a and solder alloy 31 b join, inner bump 31 isformed and semiconductor chip 10 and BGA substrate 20 are connected. Inthis embodiment, since both composition of solder alloys 31 a and 31 bis Ag:1.0 mass %, Cu:0.5 mass %, and remainder Sn, it constitutes thesame Ag:1.0 mass %, Cu:0.5 mass %, and remainder Sn as to inner bump's31 composition which joins the two and is formed.

Subsequently, under-filling resin 32 is formed like FIG. 12 by pouringin an epoxy resin between semiconductor chip 10 and BGA substrate 20(S8).

Packaging of a semiconductor device is performed (S9). That is, likeFIG. 13, on BGA substrate 20, adhesive tape 35 is used, stiffener 34 isfixed, and it equips with heat spreader 36 via heat radiation resin 37on semiconductor chip 10. At this time, on stiffener 34, adhesive tape38 is used and heat spreader 36 is fixed.

And finally the solder ball which comprises Ag:3.0 mass %, Cu:0.5 mass%, and remainder Sn is mechanically mounted on external electrode 22 ofBGA substrate 20 under surface, and outer ball 33 is formed on externalelectrode 22 by doing melting of this solder ball by reflow (S10).Thereby outer ball 33 which comprises Ag:3.0 mass %, Cu:0.5 mass %, andremainder Sn is formed, and semiconductor device 1 shown in FIG. 1 isformed.

Semiconductor device 1 is mounted in the upper surface of mountingsubstrate 40 so that outer ball 33 and connection pad 41 may touch,melting of the outer ball 33 is done by reflow, and it is made to jointo connection pad 41 at the time of actual use. As a result, as shown inFIG. 3, semiconductor device 1 is mounted on mounting substrate 40.

In this embodiment, under-filling resin is not formed between BGAsubstrate 20 and mounting substrate 40 at the time of mounting. By notforming under-filling resin, it can be prevented that the stress of alongitudinal direction occurs originating in the difference in thecoefficient of thermal expansion of under-filling resin and outer ball33, and reduction of the number of manufacturing processes and amanufacturing cost can be aimed at.

As mentioned above, the semiconductor device concerning this embodimentis provided with outer ball 33 with a comparatively high elastic moduluswith inner bump 31 with a comparatively low elastic modulus. Inner bump31 can buffer the stress resulting from the difference in thecoefficient of thermal expansion of inner bump 31 and under-fillingresin 32 by deforming according to stress. The stress concentration tothe connection portion of inner bump 31, and semiconductor chip 10 andBGA substrate 20 can be eased. When high integration of semiconductorchip 10 progresses, the area of the electric connection portion (namely,interface of first pad 11 and inner bump 31 shown in FIG. 2) to innerbump 31 in first pad 11 front surface will become small, and strengthwill fall, but by buffering stress, inner bump 31 can preventdisconnection in the portion.

Outer ball 33 can hold the stress applied from the outside as selfinternal stress. Therefore, each of each outer ball 33 can absorb thestress resulting from the difference in the coefficient of thermalexpansion of BGA substrate 20 and mounting substrate 40. The stressconcentration to outer ball 33 of the peripheral part of BGA substrate20 is eased. Therefore, disconnection between BGA substrate 20 andmounting substrate 40 can be suppressed. Thus, according to thisembodiment, the connection reliability of internal wiring and theconnection reliability with external wiring at the time of mounting ofsemiconductor device 1 can be improved.

In this embodiment, connection of BGA substrate 20 and mountingsubstrate 40 at the time of mounting is made only with outer ball 33,and under-filling resin is not formed between both. That is becauseouter ball 33 with a high elastic modulus has sufficient strength andunder-filling resin is unnecessary. The advantage that the generation ofthe stress resulting from the difference in the coefficient of thermalexpansion of the under-filling resin and outer ball 33 is prevented, andthe effect that the rise of the number of manufacturing processes and amanufacturing cost is suppressed are also acquired.

Since, as for the elastic modulus of a Sn—Ag—Cu system solder alloy, anelastic modulus becomes high as the ratio of Ag increases as statedpreviously, what is necessary is to use a solder alloy with few ratiosof Ag for inner bump 31, and just to use a solder alloy with many ratiosof Ag for outer ball 33, in applying a Sn—Ag—Cu system solder alloy asinner bump 31 and outer ball 33. When the ratio of inner bump's 31 Agwas made into 0-1.5 mass % and the ratio of Ag of outer ball 33 was doneto more than 2.5 mass % (desirably 3% or more), it turned out that theespecially excellent connection reliability is acquired by theexperiment of a present inventor. When applying a Sn—Ag—Cu system solderalloy as inner bump 31 and outer ball 33, it can contribute to leadfree-ization of a semiconductor device. However, as long as it can makeinner bump's 31 elastic modulus low and can make the elastic modulus ofouter ball 33 high, solder alloys other than a Sn—Ag—Cu system may beused.

This embodiment showed the structure which formed UBM13 and coating 24in the front surface of first pad 11, and the front surface of secondpad 21, respectively like FIG. 2. However, when the material which isexcellent in wettability with solder, and is hard to be eroded is used,for example as first pad 11 and second pad 21, the need of forming UBM13and coating 24 is lost. In that case, it may be the structure that innerbump 31 joins to first pad 11 and second pad 21 directly. It is clearthat the above-mentioned effect is acquired also in the case.

Although the thing of the three-layer structure by Ti, Cu, and Ni wasexemplified as UBM13 and the two-layer structure thing by Ni and Au wasexemplified as coating 24, respectively, it is not limited to them. Forexample, Ni free's UBM, coating of an electrode, etc. may be used.

Although screen printing of soldering paste performed the forming step(Step S3 of FIG. 3) of solder alloy 31 a to semiconductor chip 10, andthe forming step (Step S6 of FIG. 3) of solder alloy 31 b to BGAsubstrate 20 in both the above-mentioned manufacturing processes, thoseboth or one of the two may be performed by other techniques, such as anelectrolysis electroplating method. However, in an electrolysiselectroplating method, solder alloys 31 a and 31 b which comprise threeor more sorts of metal cannot be formed. Therefore, one side of solderalloys 31 a and 31 b is formed with the solder alloy which comprises Snand Ag, for example and the other is formed with the solder alloy whichcomprises Sn and Cu to form inner bump 31 of a Sn—Ag—Cu system with anelectrolysis electroplating method. At the bonding step (Step S7 of FIG.3) of subsequent semiconductor chip 10 and BGA substrate 20, meltedsolder alloys 31 a and 31 b are mixed, and inner bump 31 of a Sn—Ag—Cusystem is formed as a result.

In this embodiment, although the package structure which has stiffener34 and heat spreader 36 like FIG. 1 was shown, application of thepresent invention is not limited to this structure. For example, it maybe the structure which has only one of the two of stiffener 34 and heatspreader 36, may be the structure where it does not have both, and maybe the structure which replaced with stiffener 34 and heat spreader 36,and covered the upper surface with mold resin.

Although this invention was explained in detail, the above-mentionedexplanation is exemplification in all the aspects, and this invention isnot limited to it. The countless modification which is not exemplifiedis understood as what may be assumed without separating from the scopeof this invention.

1. A semiconductor device, comprising: a semiconductor chip; a packagesubstrate over which the semiconductor chip is mounted; a solder bumpwhich electrically connects the semiconductor chip and the packagesubstrate and which does not include Pb as a solder alloy; under-fillingresin which fills up between the semiconductor chip and the packagesubstrate; and a solder ball which electrically connects the packagesubstrate with an outside and which does not include Pb as a solderalloy; wherein the solder bump's elastic modulus is lower than anelastic modulus of the solder ball.
 2. A semiconductor device accordingto claim 1, wherein the solder bump and the solder ball includes Ag andCu, and remainder includes Sn.
 3. A semiconductor device according toclaim 2, wherein ratio of a mass of Ag in the solder bump is smallerthan ratio of a mass of Ag in the solder ball.
 4. A semiconductor deviceaccording to claim 3, wherein ratio of Ag in the solder bump is lessthan 1.5 mass %.
 5. A semiconductor device according to claim 3, whereinratio of Ag in the solder ball is more than 2.5 mass %.
 6. Asemiconductor device according to claim 1, wherein the solder bumpincludes Cu, and remainder includes Sn; and the solder ball includes Agand Cu, and remainder includes Sn.
 7. A semiconductor device accordingto claim 6, wherein ratio of Ag in the solder ball is more than 2.5 mass%.
 8. A semiconductor device according to claim 1, further comprising: amounting substrate which mounts the package substrate; wherein themounting substrate is electrically connected to the package substratevia the solder ball; and under-filling resin is not formed between themounting substrate and the package substrate.
 9. A semiconductor deviceaccording to claim 1, wherein the semiconductor chip has a first padelectrically connected with the solder bump; the package substrate has asecond pad electrically connected with the solder bump; and an electricconnection area to the solder bump in the first pad surface is smallerthan an electric connection area to the solder bump in the second padsurface.
 10. A semiconductor device according to claim 1, wherein thesemiconductor chip has a first pad electrically connected to the solderbump; the package substrate has a second pad electrically connected tothe solder bump; a predetermined first metallic film is formed in afront surface, and the first pad is connected to the solder bump via thefirst metallic film concerned; a predetermined second metallic film isformed in a front surface, and the second pad is connected to the solderbump via the second metallic film concerned; and an area of an interfaceof the first pad and the first metallic film is smaller than an area ofan interface of the second pad and the second metallic film.